"S" Process Development Agreement

Exhibit 10.54


*** Confidential treatment has been requested as to certain portions of this agreement. Such omitted confidential information has been designated by an asterisk and has been filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 under the Securities Exchange Act of 1934, as amended, and the Commission's rules and regulations promulgated under the Freedom of Information Act, pursuant to a request for confidential treatment. ***


"S" PROCESS DEVELOPMENT AGREEMENT

between

INTERNATIONAL BUSINESS MACHINES CORP.

and

ADVANCED MICRO DEVICES, INC.


This Agreement is made effective as of the 28th day of December, 2002 (hereinafter referred to as the "Effective Date") by and between International Business Machines Corporation ("IBM"), incorporated under the laws of the State of New York, U.S.A. and having an office for the transaction of business at 2070 Route 52, Hopewell Junction, NY 12533, U.S.A, and Advanced Micro Devices having an office for the transaction of business at One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 "(AMD)". IBM, and AMD may be individually referred to herein as a "Party," or collectively as the "Parties."

WHEREAS , IBM has been developing leading edge semiconductor manufacturing processes with Sony and Toshiba, and the Parties hereto desire to participate in parallel development efforts;


WHEREAS , the Parties possess complementary skills and know-how, which the Parties wish to contribute toward such process development;

WHEREAS , each Party agrees to provide certain personnel and grant the other Parties certain technology licenses in support of such process development;


WHEREAS , through the use of such complementary skills and know-how the Parties desire to achieve resource efficiencies and cost savings, and reduce the technical risk associated with the development of high end semiconductor processes in order to complete development of and put into production, leading edge high end semiconductor manufacturing processes sooner than would be possible with any of the Parties acting independently;

NOW THEREFORE , in consideration of the premises and mutual covenants contained herein, as well as for other good and valuable consideration, the receipt and sufficiency of which is hereby acknowledged, the Parties agree as follows.


SECTION 1 DEFINITIONS


Unless expressly defined and used with an initial capital letter in this Agreement, words shall have their normally accepted meanings. The headings contained in this Agreement or in any exhibit, attachment or appendix hereto are for reference purposes only and shall not affect in any way the meaning or interpretation of this Agreement. The word "shall" is mandatory, the word "may" is permissive, the word "or" is not exclusive, the words "includes" and "including" are not limiting, and the singular includes the plural. The following terms shall have the described meanings:


"Advanced Semiconductor Technology Center" or "ASTC" means the IBM 200mm or 300mm wafer process development facility used for conducting the Process Development Projects.


"Agreement" means the terms and conditions of this "S" Process Development Agreement together with any exhibits, attachments and appendices hereto.


"AMD Deputy Project Leader" means the individual, if any, appointed by AMD pursuant to Section 4.2 below.


"ASIC Product" shall mean an SOI Integrated Circuit that is not a Foundry Product and wherein all of the following conditions are met: (i) at least one of (a) the functional requirements, or (b) the design, for such SOI Integrated Circuit product is provided to a Party from a Third Party; (ii) such Party participated in an aspect of the definition and design of such product; and (iii) such Party is contractually bound to manufacture such product solely for, and to sell such product solely to, such Third Party or its distributor or other recipient solely for the benefit of such Third Party.

"Background Know-How" means methods, techniques, designs, structures, software, and specifications developed or acquired by a Party outside the performance of the Process Development Projects, which such Party provides to the other Party for use in a Process Development Project pursuant to Section 3. Such Background Know-How shall not include, Packaging Technology, Mask Fabrication and Photoresist Technology, Memory, SiGe Technology, or Chip Designs.


"BEOL" (Back End of Line) shall mean those aspects of Background Know-How and Specific Results that are directed to methods and processes of interconnecting the source, gate, or drain electrodes of FET transistors formed on a wafer, including initial passivation of such FET transistors with a dielectric, up to and not including Packaging Technology. For the avoidance of doubt, "BEOL" shall not include local interconnects made of tungsten.

"Bulk CMOS" shall mean CMOS semiconductor manufacturing technology carried out on a wafer that is not an SOI Wafer.


"Bulk CMOS Information" shall mean those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or (ii) selected by IBM either for incorporation into an IBM Bulk CMOS process or otherwise pursuant to Section 3.4.


"Chip Design(s)" shall mean any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that "Chip Designs" shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded, or (iii) other product designs as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects. For the avoidance of doubt, all of (i) through (iii) above shall be treated as Specific Results to the extent utilized in a Process Development Project.


"CMOS 10S" means a *** micron CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.1, attached hereto.


"CMOS 10S2" means a *** micron CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 10S, as further defined in Exhibit A.2.

"CMOS 11S" means a *** micron CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.3.

"CMOS 11S2" means a *** micron CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 11S, as further defined in Exhibit A.4.

"CMOS 12S" means a *** micron CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.5.

"Designated Invention" means an Invention for which a patent application has been filed by one or more of the Parties pursuant to Sections 11.1 or 11.2.


"Derivative Process(es)" shall have the meaning ascribed to it in Section 8.1

"Embedded DRAM" or "eDRAM" shall mean a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).

"Foundry Product" shall mean an SOI Integrated Circuit wherein all the following conditions are met: (i) the ***, or *** and/or ***, for such SOI Integrated Circuit product ***; (ii) *** of such product; and (iii) *** is contractually bound to ***.


"IBM Project Leader" means the individual appointed by IBM pursuant to Section 4.2, below, to provide day-to-day oversight for the Process Development Projects.

"Integrated Circuit" means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, "Integrated Circuit" shall include charge-coupled devices ("CCDs").

*** Confidential information omitted and filed separately with the Securities and Exchange Commission.


"Invention" means any invention, discovery, design or improvement, conceived or first actually reduced to practice solely or jointly by one or more Representatives of one or more of the Parties or their respective contractors during the term of this Agreement and in the performance of the Process Development Projects.


"Lithography" shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent groundrules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.


"Management Committee" shall have the meaning ascribed to it in Section 4.1.

"Mask Fabrication and Photoresist Technology" shall mean any process, procedure, Proprietary Tools (e.g. the Niagara software developed by IBM), or hardware tool used in the fabrication of photomasks, as well as the photomasks themselves, and/or the formulation and/or manufacture of photoresist; provided, however, that "Mask Fabrication and Photoresist Technology" shall not include Lithography.


"Memory" means Chip Designs and fabrication processes specifically related to read only memory (ROM), dynamic random access memory (DRAM), programmable ROMs, magnetic RAM (MRAM), ferroelectric RAM, and Embedded DRAM. For the avoidance of doubt, "Memory" shall not include static RAM (SRAM) macros utilized in the Process Development Projects as test vehicles.


"Net Selling Price" for each unit of a particular ASIC Product means the net revenue recorded by AMD (including Wholly Owned Subsidiaries and Related Subsidiaries of AMD) with respect to an ASIC Product less (a) shipping, (b) insurance, and (c) sales, value added, use or excise taxes, to the extent to which they are actually paid or allowed, and less allowances to the extent they are actually allowed. If ASIC Products are sold, leased or otherwise transferred in a higher level of assembly or in the course of a transaction that includes other products or services with no separate bona fide price to be charged for the ASIC Products, the applicable Net Selling Price for the purpose of calculating royalties shall be the fair market value of the ASIC Product, but no less than the average Net Selling Price of all such units of other ASIC Products sold, leased, or otherwise transferred to a Third Party by AMD (and/or by Wholly Owned Subsidiaries and Related Subsidiaries of AMD), whichever the case may be, during the preceding half year.

"Packaging Technology" shall mean any process, procedure, software, or hardware tools used in the packaging of integrated circuit products into single-chip packages, multi-chip packages, or any other higher levels of assembly, including but not limited to IBM's collapsible chip carrier

connection ("C4") interconnect technology; provided, however "Packaging Technology" shall not include the formation of layers on a wafer up to and including the final via layer (referred to as LV, TV, or FV level), but shall include any process, procedure, or practice subsequent to such step.


"Process Development Project(s)" means the CMOS 10S, CMOS 10S2, CMOS 11S, CMOS 11S2, and CMOS 12S development work conducted jointly by Representatives of the Parties pursuant to the terms and conditions of this Agreement, as more fully set forth in Section 3.1, below.


"Project Leaders" means the IBM Project Leader and the AMD Deputy Project Leader.

"Proprietary Tools" means software (in source code form or in object code form), models and/or data, and other instrumentalities that are not commercially available and are either owned by a Party or under which a Party has the right to grant royalty-free licenses, and that are used in Process Development Projects.


"Qualification" means the T2 date identified in the schedule for each Process Development Project, as set forth in Exhibit B.


"Related Subsidiary" shall mean a corporation, company or other entity:

(a) one hundred percent (100%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto; or

(b) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity one hundred percent (100%) of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto;

provided that in either case, such entity shall be considered a Related Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to the Related Subsidiary, only so long as such ownership or control exists.

"Representative(s)" means, a Party's employees and employees of a Party's Wholly Owned Subsidiaries.


"Semiconductor Product" means a component that contains an Integrated Circuit on a single or multichip module that incorporates a means of connecting those Integrated Circuits with other

electronic elements (active or passive) and/or means to make external electrical connections to such elements, but which excludes any means for a user to operate the functions therein (e.g., buttons, switches, sensors).


"Silicon-Germanium Technology" or "SiGe Technology" shall mean semiconductor fabrication processes and design techniques incorporating silicon and germanium layers, provided, however, "SiGe Technology" shall not include strained silicon channel MOSFET techniques carried out on SOI Wafers.


"Silicon-On-Insulator Wafer" or "SOI Wafer" shall mean a, single-crystal silicon wafer bearing a horizontally-disposed isolating silicon dioxide (SiO 2 ) layer, in turn bearing a single-crystal silicon layer or a polysilicon layer, which is separated from the underlying silicon by the silicon dioxide layer and in which one or more active or passive integrated circuit structures are formed.


"SOI Device Information" means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on commercially available SOI Wafers other than Bulk CMOS Information.


"SOI Integrated Circuit" shall mean an Integrated Circuit fabricated utilizing SOI Device Information and built on SOI Wafers.


"Specific Results" shall mean information and items, other than i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, and vi) Chip Designs, developed and/or contributed to the Process Development Projects by the Parties pursuant to the development work of the Process Development Projects as follows:


The documentation produced for the Process Development Projects as set forth in Exhibit J attached hereto ("Documentation");


All information and items resulting from the Process Development Projects, including but not limited to methods, techniques, unit processes, process flows, structures in silicon, test software, and specifications for equipment, chemicals, masks and consumables;


Any Background Know-How provided to the Process Development Project(s) by a Party pursuant to Section 3, below.


"Subsidiary" means a corporation, company or other entity:

(a) more than fifty percent (50%) of whose outstanding shares or securities (representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party hereto, or

(b) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, but more than fifty percent (50%) of whose ownership interest representing the right to make the decisions for such corporation, company or other entity is now or hereafter, owned or controlled, directly or indirectly, by a Party hereto,


provided that in either case such entity shall be considered a Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Subsidiaries, only so long as such ownership or control exists.

"Technical Coordinators" means the individuals referred to in Section 4.4, below.

"Term" means the period of time from the Effective Date and ending on December 31, 2005.

"Test Site" means a device or circuit evaluation site on a wafer.


"Third Party" or "Third Parties" means an entity or entities other than the Parties or their Wholly Owned Subsidiaries or Related Subsidiaries.


"Wholly Owned Subsidiary" shall mean 1) a corporation, company or other entity:

(a) one hundred percent (100%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party; or

(b) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity but one hundred percent of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by a Party;

provided that in either case such entity shall be considered a Wholly Owned Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Wholly Owned Subsidiaries, only so long as such ownership or control exists; or 2) a corporation, company or other entity:

(c) at least seventy five percent (75%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party; or

(d) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity but at least seventy five percent (75%) of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by a Party;


provided, that in either case (c) or (d) above, (i) all of the remaining such ownership interest is solely owned or controlled, directly or indirectly, by one or more corporations, companies or other entities which are purely financial investors who are not engaged in the design, development, manufacture, marketing or sale of Semiconductor Products, and (ii) such entity shall be considered a Wholly Owned Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Wholly Owned Subsidiaries, only so long as such ownership or control exists.


SECTION 2 ASTC


IBM has established the Advanced Semiconductor Technology Center in East Fishkill, New York. IBM shall be responsible for the operations of the ASTC, including, but not limited to capacity, staffing, and capital purchases. Process Development Projects shall be conducted primarily at the ASTC. In addition to the ASTC, IBM may utilize other IBM facilities to conduct elements of the development work associated with the Process Development Projects. In addition, the Parties may mutually agree to utilize AMD development facilities for specifically defined elements of the Process Development Projects. If the Management Committee members so agree, such agreement shall be documented in writing and signed by the Parties.

SECTION 3 SCOPE OF PROCESS DEVELOPMENT PROJECTS 3.1 The Parties agree to jointly develop semiconductor manufacturing process technology based on IBM's "S" high performance technology roadmap on commercially available SOI Wafers that meet the requirements set forth as "Strategic Technology Objectives" in Exhibit A (hereinafter referred to as "Strategic Technology Objectives") in accordance with the schedule set forth in Exhibit B (hereinafter referred to as "Development Schedule"). The Parties agree that the process technology so developed, shall be high performance, leading edge technology and, to the extent consistent with the Strategic Technology Objectives, shall be cost efficient. Any modification to such Strategic Technology Objectives or Development Schedule requires the mutual agreement of the Parties. For the avoidance of doubt, none of the Process Development Projects shall include the development of i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, or vi) Chip Designs.

3.2 The Parties agree that Exhibit A also sets forth the potential technology implementation options for each Process Development Project. The Parties shall work together to evaluate the various options available, including individual process module feasibility, integration, characterization and qualification. The goal of such evaluation is to agree on an integrated process technology that meets the Strategic Technology Objectives. If the Project Leaders are unable to agree on a particular process module to be developed, or should they disagree as to continued development of a process module that was previously selected, the process module preferred by IBM shall be pursued in the applicable Process Development Project.

3.3 For information other than that developed by the Parties in a given Process Development Project to be considered Specific Results for that Project, including Background Know-How, it must be either deliberately provided to the Process Development Projects by the owner of such information, or be evaluated by the Project Leaders, pursuant to Section 3.2, for possible use in a Process Development Project . In the event such item of information is provided, and the Party owning such information notifies the Project Leaders within thirty (30) days after such owning Party's disclosure or the initiation of such evaluation that such information should be withdrawn, such owning Party may withdraw such information from use in the Process Development Projects and all such information in tangible form associated therewith shall be returned to such owning Party and such tangible information shall not become Specific Results. In the event of such withdrawal, any non-tangible information related to such information retained in the minds of the non-owning Party's employees shall be treated as Specific Results by the non-owning Parties. Absent such notice and withdrawal within thirty (30) days, all information deliberately provided by the owner of such information or evaluated by the Project Leaders shall be treated as Specific Results.

3.3.1 Any issue as to whether information was deliberately provided to the Process Development Projects shall be resolved by the Project Leaders based on either of the following criteria:

3.3.1.1 whether the information was deliberately exposed to the other Parties by a Representative of the owner of such information; or 3.3.1.2 whether the evaluation of the information by the Representatives was validly considered for incorporation into the Process Development Projects.


If the Project Leaders cannot agree, such issue shall be resolved by the Management Committee in accordance with the criteria in Sections 3.3.1.1 and 3.3.1.2.

3.3.2 Each Party shall be responsible for instructing its Representatives on methods of proper introduction of information into the Process Development Projects, and the consequences under Section 7.10, below, of information that is inadvertently obtained.

3.4 During a given Process Development Project, the IBM Project Leader shall designate elements of the Specific Results and Background Know-How thereof that IBM will be applying toward development of its applicable Bulk CMOS process. IBM shall provide an initial designation of such elements at the completion of its initial feasibility studies for the applicable Process Development Project (set forth in Exhibit B as the "T-Bulk date"), and IBM shall provide a final designation of such elements no later than the "T1" date for the applicable Process Development Project, as set forth in Exhibit B. AMD agrees that IBM reserves the right to change such designations between its initial designation and its final designation. In either case, prior to making such determinations IBM shall consult with AMD, who shall provide its input as to the applicability of such elements to a Bulk CMOS process; provided, however, that IBM shall have the right to make any and all final decisions as to designation and application of such elements to its Bulk CMOS process.

3.5 Each Party shall have access to all Specific Results and shall be solely responsible, including the cost therefor, for the transfer of Specific Results to its own facilities. In addition to Representatives, AMD may assign additional personnel to IBM facilities to assist with such transfer. The number of additional personnel and the duration of their assignment shall be mutually agreed to by the Management Coordinators. As part of each Process Development Project, the Project Leaders shall coordinate the completion of the Documentation for such Process Development Project and each Party shall have access to all such Documentation. Notwithstanding the foregoing, since the T1 and T2 dates for CMOS 12S, as set forth in the Development Schedule, are outside of the Term, only a subset of the Documentation shall be prepared for the CMOS 12S Process Development Project, as determined by the Project Leaders. Should AMD have any questions regarding the Documentation as they are transferring such Specific Results to their own facilities, IBM ...